1. Field of the Invention
The present invention relates to a semiconductor memory device, and particularly a semiconductor memory device in which sense amplifier circuits for sensing and amplifying memory cell data are provided corresponding to respective columns. More particularly, the invention relates to a structure for reducing an access time in a clock synchronous semiconductor memory device operating in synchronization with a clock signal.
2. Description of the Background Art
FIG. 40 schematically shows a structure of an array of a conventional semiconductor memory device. In FIG. 40, a memory cell MC is arranged corresponding to a crossing between a bit line pair BLP and a word line WL. Memory cells MC are arranged in rows and columns. Bit line pairs BLP are arranged corresponding to the memory cell columns, respectively. Word lines WL are arranged corresponding to the memory cell rows, respectively. FIG. 40 shows only one bit line pair BLP and one word line WL representatively. Bit line pair BLP includes bit lines BL and ZBL. In bit line pair BLP, only one of bit lines BL and ZBL is connected to memory cell MC. In FIG. 40, memory cell MC connected to bit line BL is shown representatively. Memory cell MC includes a memory cell capacitor MS for storing information and an access transistor MT turned on in response to a signal potential on word line WL for coupling the memory cell capacitor MS to corresponding bit line BL (or ZBL). Access transistor MT is formed of an n-channel MOS transistor (insulated gate field-effect transistor).
Bit line pair BLP is provided with a sense amplifier circuit SA which in turn is activated in response to a sense amplifier activating signal .phi.SAE for differentially amplifying the potentials on bit lines BL and ZBL, and a column select gate YG for electrically coupling bit lines BL and ZBL to an internal data line pair IOP in accordance with a column select signal CSL. Internal data line pair IOP includes internal data lines I/O and ZI/O for transmitting complementary signals. Internal data line pair IOP is coupled to an input/output circuit NSK. Operation of the semiconductor memory device shown in FIG. 40 will now be described with reference to a signal waveform diagram of FIG. 41.
In a standby cycle, bit lines BL and ZBL are precharged and equalized to an intermediate voltage. Word line WL is in an unselected state, and access transistor MT in memory cell MC is in the off state. Column select signal CSL is at L-level of the unselected state, and column select gate YG is in the off state.
When a memory cycle starts, bit lines BL and ZBL are electrically floated at the precharge voltage. Then, word line WL corresponding to an addressed row is driven to a selected state in accordance with the address signal, and has the voltage level thereof raised. In accordance with this rising of potential on word line WL, access transistor MT included in memory cell MC is turned on and the information stored in memory cell capacitor MS is read onto corresponding bit line BL or ZBL. FIG. 41 shows by way of example a signal waveform in the case where the data at L-level is read onto bit line BL.
When bit line BL is connected to the memory cell, bit line ZBL does not receive the memory cell data, but maintains the precharge voltage level.
When the potential difference on bit line pair BLP sufficiently increases, sense amplifier activating signal .phi.SAE is then activated so that sense amplifier circuit SA differentially amplifies the voltages on bit lines BL and ZBL. This sensing operation of sense amplifier circuit SA decides the voltages on bit lines BL and ZBL to H- and L-levels in accordance with the storage information of memory cell MC.
When sense amplifier circuit SA completes the sensing operation, a column selecting operation is then performed. In the column selecting operation, a column decoder (not shown) drives column select signal CSL corresponding to an addressed column to the H-level of the active state to turn on a column select gate YG, and bit line pair BLP arranged corresponding to the addressed column is electrically coupled to internal data line pair IOP. In accordance with the signals on the internal data lines, input/output circuit NSK produces read data DQ to be externally read. In the data write operation, input/output circuit NSK drives internal data line pair IOP to transmit the write data to bit line pair BLP via selected column select gate YG.
The semiconductor memory device with a memory cell MC of a one transistor and one-capacitor structure described above is called a dynamic semiconductor memory device (referred to as a "DRAM" hereinafter), and is suitable for achieving high density and high integration because the memory cell occupies a small area.
In the DRAM, however, a capacitance value of memory cell capacitor MS is small, and the voltage difference produced on bit line pair BLP is small in the operation of reading memory cell data. Further, the storage data of a memory cell is destructed when the data is read from the memory cell. Therefore, it is necessary to use sense amplifier circuit SA for amplifying the read data and rewriting the original data into the memory cell.
If the column selection is performed before the bit line voltage becomes stable after sense amplifier circuit SA starts the sensing operation, connection between the internal data lines and the selected column causes variations in voltages on the bit line pair of the selected column. Accordingly, the sense amplifier circuit may malfunction, and the memory cell data may not be accurately read out. Therefore, a period from a time ta when the row selection is performed to a time when the column selection is enabled is usually called a "column interlock period", during which the column selecting operation is inhibited (see FIG. 41). In the DRAM, this period is referred to as a RAS-CAS delay time tRCD, and a finite time is required for the period from the time when a row access for the row selection is instructed to the time when a column access for the column selection is performed.
In the data write operation, a particular problem does not occur even if the memory cell data of a selected column is destructed (the write data is transmitted to the memory cell). However, for providing the same column access timing in both the data read operation and the data write operation, the column selecting operation can be performed only after completion of the operation of the sense amplifier circuit in both the data read mode and the data write mode. Therefore, an access time (RAS access time) tRAC between execution of the row access and subsequent actual external reading of the memory cell data cannot be reduced, and fast access cannot be performed.
Recently, clock synchronous semiconductor memory devices which perform writing and reading of data in synchronization with the clock signal have been in practical use. In this clock synchronous semiconductor memory device, the operation mode is designated by a command applied in synchronization with the clock signal. In this clock synchronous semiconductor memory device, writing and reading of data are performed in synchronization with the clock signal, but the structure of the memory cell array is substantially the same as a standard DRAM.
FIG. 42 shows an example of a command application sequence of the clock synchronous semiconductor memory device. In FIG. 42, a row access command RACT for activating the row selection and a column access command CACT of instructing the column selection and write/read of data are each applied at the rising edge of a clock signal CLK1. Column access command CACT can be applied after elapse of time tRCD from application of row access command RACT. In the clock synchronous semiconductor memory device operating in synchronization with clock signal CLK1, therefore, the time tRCD is equal to a period of two clock cycles.
In the case where the clock synchronous semiconductor memory device operates in synchronization with a fast clock signal CLK2, time tRCD is equal to a period of four clock cycles of clock signal CLK2. Accordingly, even if the operation is performed in synchronization with fast clock signal CLK2, time tRCD cannot be reduced so that fast access cannot be achieved.